HAYWARD, Calif.--()--Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.0. The newly updated version of Averant’s flagship product provides exceptional functionality, including integrated timing constraints checking as a standard feature, and offers significant improvements to earlier versions of the software.
“Release 6.0 adds timing constraints verification to an already extensive array of tools including property verification, sequential equivalency checking, automatic checks, static coverage and semi-formal bug hunting.”
Averant, a pioneer in the design automation industry, creates tools that are easily adopted into the design flow and help improve quality, reduce risk, and speed the design process. Solidify 6.0 builds on the company’s innovative product line and strengthens the firm’s position as a leader in the field.
“Averant is committed to providing an integrated environment of high-performance formal verification tools,” said Ramin Hojati, president of Averant. “Release 6.0 adds timing constraints verification to an already extensive array of tools including property verification, sequential equivalency checking, automatic checks, static coverage and semi-formal bug hunting.”
Additional highlights of the release include:
- Improved SEC. The sequential equivalency checking (SEC) feature of Solidify has been in production use in power reduction flows for over a year. During this time, a number of user requested enhancements were implemented and integrated.
- Improved Clock Crossing. The clock-crossing checks have been rewritten taking better advantage of Solidify’s multi-clock property verification engines.
- Improved X-Management Checks. Nearly a decade ago, Solidify pioneered X-management RTL checks in collaboration with top multi-national semi-conductor firms. Solidify 6.0 adds new functionality for ensuring that undesired X’s do not reach outputs, and for identifying simulation versus synthesis mismatches.
- Improved Engines and Support. Solidify 6.0 offers enhanced engines along with better System Verilog Design support for a more optimized user experience.
Solidify 6.0 is in customer testing stage and is scheduled for release later this Fall.
Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s signature product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. For more information, visit http://www.averant.com.