Analog Bits Continues to Drive Innovation for 0.25 micron to 20 nm IC Designs Using Tanner EDA Schematic Capture and Layout Tools

L-Edit™ and S-Edit™ provide modular, robust solution for entire line of low-power, customizable analog IP

MONROVIA, Calif.--(BUSINESS WIRE)--Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), has been providing schematic capture and layout solutions to Analog Bits since 1995. When Analog Bits, the leader in integrated clocking and interface IP, recently migrated their products from a 28nm to 20nm manufacturing process, Tanner EDA’s robust tools were able to meet the new layout methodology and continue to provide the usual high quality solutions.

“The market tells us that, starting at 28 nm, analog layout becomes about 3-5x more complicated for IC design”

“As process nodes shrink, electromigration is becoming a bigger and bigger problem,” said Mahesh Tirupattur, executive vice president at Analog Bits. “Metals become thinner and narrower, so that more sophisticated wiring is needed, making layout more complex. Layout-driven design is now vital to see how power distribution should be implemented. Fortunately, Tanner EDA's L-Edit and S-Edit tools have been able to keep up with our 20nm methodology, giving us the quality we are used to and helping us speed time to market. We always appreciate not needing to have a CAD engineer on hand to implement and manage every aspect of our EDA tools. Tanner EDA tools are individualized and modular. Everyone has dedicated licenses available and changes are easy to manage. The tool flow remains steady and dependable, with consistent user interfaces contributing to ease of use.”

S-Edit™ is Tanner EDA’s easy-to-use design environment for schematic capture, giving design engineers the power needed to handle the most complex full-custom IC design capture. L-Edit™ is Tanner EDA’s complete hierarchical physical layout editor. L-Edit combines fast rendering and built-in productivity tools to allow engineers to maximize efficiency when creating and laying out a design.

“The market tells us that, starting at 28 nm, analog layout becomes about 3-5x more complicated for IC design,” said John Zuk, vice president of marketing and business strategy at Tanner EDA. “This has not fazed Analog Bits, which recently increased its customer base and expanded its engineering facilities and support staff to keep up with demand for their broad portfolio of differentiated SERDES, PLL and Interface IP products. We’re glad to continue to provide them with tools to help their customers accelerate time to volume and to increase product differentiation.”

About Tanner EDA

Tanner EDA provides a complete line of software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

HiPer Verify, HiPer Silicon, Tanner Tools, L-Edit, S-Edit and W-Edit are trademarks of Tanner Research, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.