EL DORADO HILLS, Calif.--(Multicore Association™, a global non-profit organization that develops standards to speed time-to-market for products with multicore processor implementations, has announced the availability of its Multicore Task Management Application Program Interface (MTAPI) that supports the coordination of tasks on embedded parallel systems.)--After 1.5 years of working-group effort, the
“MTAPI greatly simplifies the programming challenge to optimize task management and parallel programming on complex SoCs supporting heterogeneous architectures and hardware acceleration units”
To fully utilize homogeneous and/or heterogeneous multicore processors or systems-on-chip (SoCs), a programmer must develop software that splits a program into tasks that can be executed concurrently on different processor cores. Today’s operating systems and runtime libraries for embedded systems provide threads or thread-like mechanisms that are not suited for the fine-grain parallelism required by multicore architectures, typically because the coordination of hundreds or thousands of parallel tasks generates too much overhead relative to the actual computation time. The programming model prior to MTAPI, required complex, low-level synchronization and programming with threads, was limited to single operating systems running on single homogeneous multicore processors.
The MTAPI specification eliminates these obstacles by providing an API allowing programmers to develop parallel embedded software with familiar programming processes. MTAPI features include runtime scheduling and mapping of tasks to processor cores. Optionally, the MTAPI implementation provides access to hardware-implemented actions and/or queues to take advantage of processor-specific features and to increase performance.
Unlike existing APIs that provide task management functionality (e.g. OpenMP, TBB, Cilk, OpenCL), the MTAPI specification allows implementations for resource-constrained embedded systems, such as those with a small memory footprint, deterministic behavior, and allow for hardware-specific optimizations. Furthermore, portability is essential for the implementation. MTAPI will support different processor architectures and can be implemented in plain C language programing on top of different operating systems or as a bare-metal solution. In short, MTAPI supports asymmetric multiprocessing at the hardware and software level.
Urs Gleim, head of the Parallel Systems research group at Siemens AG, Corporate Technology, in Germany, is chairing the MTAPI Working Group, with technical experts participating from industry and academia including: ENEA, Freescale Semiconductor, Institut National des Sciences Appliquées de Rennes, Qualcomm, Plurality, PolyCore Software, Siemens, Texas Instruments, University of Houston, and Wind River.
“MTAPI greatly simplifies the programming challenge to optimize task management and parallel programming on complex SoCs supporting heterogeneous architectures and hardware acceleration units,” said Urs Gleim. “In addition to its support for portability across multicore processor platforms, MTAPI’s dynamic runtime support will allow the implementer to optimize for quality of service as well as power management that is based on real-time performance demands.”
“MTAPI is aligned with our previously released specifications, Multicore Resource Management API (MRAPI) and the Multicore Communications API (MCAPI). As a matter of fact, MRAPI can be used as part of MTAPI’s internal portability layer, and similarly, the MCAPI may be used for inter-node communications,” said Markus Levy, Multicore Association president. “On a different note, I’d like to thank Mr. Gleim and the members of the working group for their efforts on this project and for recognizing the great value that MTAPI will bring to the industry.”
The MTAPI specification is available for free download from the Multicore Association website. In addition, MCA is providing an MTAPI overview document (called the MTAPI Nutshell) and a detailed reference card. Inquiries regarding membership in the Multicore Association and participation in any working group can be made to Markus Levy (firstname.lastname@example.org).
About The Multicore Association
The Multicore Association provides a neutral forum for vendors who are working with and/or proliferating multicore-related products, including processors, infrastructure, devices, software, and applications. The consortium has made available its Multicore Communications API (MCAPI), Multicore Resource Management API (MRAPI), and Multicore Task Management API (MTAPI) specifications, and its Multicore Programming Practices Guide (MPP) through its website. The consortium also has a working group (TIWG) defining a common data format and creating standards-based mechanisms to share data across diverse and non-interoperable development tools for homogeneous and heterogeneous multicore systems, specifically related to the interfaces between profilers and analysis/visualization tools.
Members include Abo Akademi University, Advanced Cluster Systems, Broadcom, Carnegie Mellon University, Cavium Networks, Codeplay, Delft University of Technology, EADS, Ecole Polytechnique de Montreal, EfficiOS, Enea, Ericsson, eSOL, Freescale Semiconductor, Huawei, Institute of Electronics and Telecommunications of Rennes, LG Electronics, Lockheed Martin, LSI, Mentor Graphics, MIPS Technologies, National Instruments, nCore Design, Netronome, Nokia Siemens Networks, PolyCore Software, Qualcomm, Sage Electronic Engineering, Siemens AG, Tampere University of Technologies, Texas Instruments, Timing Architects, UAS Technikum Wien, University of Houston, and Wind River. Further information is available at www.multicore-association.org.
Word copy of release
You can tweet or share the release directly from the Multicore Association Press Center on HughesCom’s website. The release and background materials are also available for download.